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| SN54/74LS164 SERIAL-IN PARALLEL-OUT SHIFT REGISTER The SN54 / 74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL products. SERIAL-IN PARALLEL-OUT SHIFT REGISTER LOW POWER SCHOTTKY * * * * * * Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 14 1 J SUFFIX CERAMIC CASE 632-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 Q7 13 Q6 12 Q5 11 Q4 10 MR 9 CP 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 A 2 B 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD PIN NAMES A, B CP MR Q0 - Q7 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) LOADING (Note a) HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. Ceramic Plastic SOIC LOGIC SYMBOL 1 2 8 A LS164 B 8-BIT SHIFT REGISTER CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 34 5 6 10 11 12 13 NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-1 SN54/74LS164 LOGIC DIAGRAM 1 2 A D B CD CD CD CD CD CD CD CD CP MR VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q0 3 Q D Q D Q D Q D Q D Q D Q D Q 8 9 Q1 4 Q2 5 Q3 6 Q4 10 Q5 11 Q6 12 Q7 13 FUNCTIONAL DESCRIPTION The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH, or both inputs connected together. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A*B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. MODE SELECT -- TRUTH TABLE OPERATING MODE Reset (Clear) Shift INPUTS MR L H H H H A X I I h h B X I h I h OUTPUTS Q0 L L L L H Q1-Q7 L-L q0 - q6 q0 - q6 q0 - q6 q0 - q6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don't Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA FAST AND LS TTL DATA 5-2 SN54/74LS164 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 -100 27 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V 2.5 - 0.65 3.5 V 0.8 - 1.5 V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIH or VIL per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay MR to Output Q Propagation Delay Clock to Output Q Min 25 Typ 36 24 17 21 36 27 32 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol tW ts th trec Parameter CP, MR Pulse Width Data Setup Time Data Hold Time MR to Clock Recovery Time Min 20 15 5.0 20 Typ Max Unit ns ns ns ns VCC = 5.0 V Test Conditions FAST AND LS TTL DATA 5-3 SN54/74LS164 AC WAVEFORMS *The shaded areas indicate when the input is permitted to change for predictable output performance. I/fmax 1.3 V CP tPHL Q 1.3 V CONDITIONS: MR = H tPLH 1.3 V tW 1.3 V 1.3 V MR 1.3 V tW 1.3 V trec 1.3 V CP tPHL Q 1.3 V Figure 1. Clock to Output Delays and Clock Pulse Width Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time 1/fmax tW CP 1.3 V ts(H) D * 1.3 V 1.3 V 1.3 V ts(L) 1.3 V 1.3 V th(H) 1.3 V th(L) 1.3 V Q 1.3 V 1.3 V Figure 3. Data Setup and Hold Times FAST AND LS TTL DATA 5-4 |
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